The present invention relates to a manufacturing process for a semiconductor device such as an IC, a sputtering target for a metal silicide wiring pattern and a manufacturing process for the sputtering target.
FIGS. 4a-4e show a conventional process for forming an FET gate on a silicon substrate and for contacting the gate 10 with a wiring pattern on an upper layer via a contact hole. As shown in FIG. 4(a), 7 through 15 nm in thickness of a gate oxide layer 2 is formed on a surface of a silicon substrate 1 through the thermal oxidation process, and poly-silicon is deposited by CVD (chemical vapor deposition) and doped with phosphorus (P) or arsenic (As) in an ion implantation process in order to form a doped poly-silicon layer 3. Then, a metal silicide having a high melting point such as tungsten silicide (WSi) is formed on the poly-silicon layer in CVD or the sputtering, method, thereby forming a first wiring pattern layer 4.
A gate G is, as shown in FIG. 4(b), formed on the stacked layers through the photo lithography process and an insulator film 5 is formed by thermal oxidation at 800 to 900xc2x0 C. Subsequently, as shown in FIG. 4(c), BPSG (borophosphosilicate glass) is deposited by CVD and a first insulator layer 6 is formed through the thermal oxidation. A contact hole 7 is opened through the first insulator layer 6 and the insulator film 5 on the gate. A poly-silicon film is formed by CVD, as shown in FIG. 4(c), and phosphorus (P) is diffused or arsenic (As) is doped by ion implantation into the poly-silicon 5 film to form a second wiring pattern layer 8. Then, an electrode pattern is formed on the second wiring pattern layer 8 in a photo lithography process. Finally, as shown in Fig. of 4(e), a BPSG layer is formed by CVD and the formed layer is thermally treated to form a second insulator layer 9.
In the conventional wiring process, however, since the thermal treatment for forming the second insulator layer 9 causes diffusion of the dopant such as phosphorus (P) or arsenic (As) into the first wiring pattern player 4 from the second wiring pattern layer 8, it increases, the contact resistance between the first and second wiring pattern layers 4, 8, and the predetermined transistor properties cannot be achieved due to failing of the ohmic contact.
Further, when the first wiring pattern layer 4 is formed in the sputtering method, abnormal discharge occurs due to charge-up of silicon included in the sputtering target. Thus the silicon is scattered on the wafer as particles, and they may cause an unnecessary short-circuit. The sputtering target for forming the first wiring pattern layer 4 is a mixture of tungsten (W) and silicon (Si) whose molar ratio W:Si is 1:2.6 to 1:2.8. The molar ratio of tungsten silicide (WSi2) as a pure compound is 1:2. The sputtering target is produced by mixing tungsten silicide with silicon particles and by baking the mixture under high-pressure. Since the mixed silicon particles has exceedingly low conduction, it causes charge-up in a well-used DC magnetron sputtering method.
The present invention has been accomplished in view of to the above problems, and it is a first object of the invention to provide a process for manufacturing a semiconductor device that can prevent the increment of the contact resistance due to diffusion of dopant from the second wiring pattern layer to the first wiring pattern layer (a metal silicide layer) during a thermal treatment of an insulator layer.
Furthermore, a second object of the present invention is to provide a sputtering target that can prevent particles due to charge-up and a manufacturing method thereof.
According to a first aspect, there is provided a process for manufacturing a semiconductor device comprising: a first wiring pattern forming step in which a first wiring pattern layer is formed from metal silicide including dopant; an insulator layer forming step in which an insulator layer is formed to cover the first wiring pattern layer; a contact hole forming step in which a contact hole is formed through the insulator layer; a second wiring pastern forming step in which a second wiring pattern including dopant is formed for covering the insulator layer as well as the contact hole; and wherein the concentration of the dopant in the first wiring pattern layer equals or is larger than that in the second wiring pattern layer.
With this process, the balance of the concentration of the dopant prevents the diffusion of the dopant from the second wiring pattern layer to the first wiring pattern layer during thermal treatment after forming the second wiring pattern layer, thereby the first object is achieved.
The dopant is injected into the first wiring pattern layer at the time of or after forming the first wiring pattern layer. When the first wiring pattern layer is formed by a sputtering method, a metal silicide including dopant is used as the sputtering target. When the first wiring pattern layer is formed by CVD, at least two kinds of gas are selected so that a metal silicide layer including metal, silicon and dopant is formed through chemical reaction.
If the metal silicide including the dopant is used as a sputtering target, it reduces the generation of particles due to charge-up even when a DC magnetron sputtering device is used, and thereby the second object is achieved. Such a sputtering target may be produced by a physical process by baking metal silicide particles under high-pressure or by a chemical process using CVD. The physical process to produce the sputtering target comprises a step to make doped silicon particles by adding dopant to silicon, a step to produce metal silicide particles from the doped silicon particles and metal through thermal reaction, and a step to bake the metal silicide particles under high-pressure or to bake the metal silicide particles and the doped silicon particles under high-pressure. In the chemical process to produce the sputtering target, at least two kinds of gas are selected so that metal silicide layer including metal, silicon and dopant is formed on a base plate through chemical reaction.
In the case when the dopant included in the first wiring pattern layer is added after the first wiring pattern layer has been formed, the process comprises a step for forming a metal silicide layer without dopant and a step for adding the dopant to the metal silicide layer. The dopant may be diffused into the metal silicide layer from a layer that is in contact with the metal silicide layer or may be directly injected into the metal silicide layer by ion implantation.
In order to diffuse the dopant from the contact layer, there may comprise a step for forming a doped silicon layer on the metal silicide layer, and a step of a thermal treatment to oxidize the doped silicon layer and to diffuse the dopant included in the doped silicon layer into the metal silicide layer. Further, the first wiring pattern may be formed by the photo lithography process (a patterning step) before or after the formation of the doped silicon layer.
According to a second aspect, there is provided process for manufacturing a semiconductor device comprising: a first wiring pattern forming step in which a first wiring pattern layer is formed from metal silicide without dopant; an insulator layer forming step in which an insulator layer is formed to cover the first wiring pattern layer; a contact hole forming step in which a contact hole is formed through the insulator layer; a second wiring pattern layer forming step in which a second wiring pattern including dopant is formed by CVD with controlling flow of addition gas so that the concentration of the dopant gradually decreases with growth of the layer for covering the insulator layer as well as the contact hole proceeds; a diffusing step in which the dopant included in the second wiring pattern layer is diffused into the first wiring pattern layer; and wherein the concentration of the dopant at the time of forming the second wiring pattern layer is designed so as to obtain good contact between the first and second wiring pattern layers after the diffusion step.
The second aspect admits the diffusion of the dopant from the first wiring pattern layer to the second wiring pattern layer. In the prior art, such a diffusion was a defect to increase contact resistance. The difference between the second aspect and the prior art is the initial concentration of the dopant in the second wiring pattern layer. That is, the concentration of the dopant in the second wiring pattern layer is high enough to keep a sufficient concentration after diffusion.
FIGS. 1a-1e show sectional views in each of steps of the process for manufacturing a semiconductor device according to the first embodiment.
FIGS. 2a-2e show sectional views in each of steps of the process for manufacturing a semiconductor device according to the fourth embodiment.
FIGS. 3a-3e show sectional views in each of steps of the process for manufacturing a semiconductor device according to the fifth embodiment.
FIGS. 4a-4e show sectional views in each of steps of the process for manufacturing a semi conductor device according to the prior art.